It will be recognized by one skilled in the art that logic signals which are the inverse of each other are conventionally referred to as "signal" and "not-signal", meaning that when "signal" is a logical "1" (or "True"), then "not-signal" is a logical "0" (or "False"). It is conventional in schematics to indicate "not-signal" by the name of the signal with a line or bar over it, and this convention is followed in the figures. For typographical reasons, however, in this specification the inverse functions will be referred to as "not-(function)". Thus, it will be understood that "not-SELECT" in the following description is the same signal as "SELECT with a bar over it" in the figures.
In numerous CMOS designs it is important to control the logic levels of a control signal for analog functions to levels other than the power supplies. One instance where such logic level shifting is required is in high-speed current-mode digital-analog (D/A) converters. By operating a differential switch pair in saturation, glitches are reduced significantly.
FIG. 2 shows a portion of such a D/A converter for illustration. Field Effect Transistor (FET) devices (21) and (22) control outputs (20) which lead to additional switches, current sinks, etc., the nature of which is not material to this discussion.
The logic signals SELECT and not-SELECT are required to allow FETs (21) and (22) to remain either cut-off or in saturation, never in triode region, in order to reduce current glitches at the D/A output (20).
Previously, the circuit of FIG. 3 was commonly used to generate the logic level signals SELECT and not-SELECT. The input to the circuit of FIG. 3 is the control signal CMOS and its inverse not-CMOS. These signals control the gates of N-channel FETs (31) and (32), respectively, to switch the current source (30) through four diodes (33), (34), (35) and (36) and then through diode (37) to ground.
It should be noted, as shown in FIG. 3a, that in the circuit of FIG. 3, diodes (33) through (37) are usually implemented as N-channel FETs (39) with common gate-drain connections. The logic low level is set by the gate-source voltage (V.sub.gs) for device (37), and the logic high level is set by V.sub.gs for device (37), and for devices (33) and (35) or (34) and (36), depending on the status of CMOS and not-CMOS. For simplicity, these FETs will continue to be referred to as "diodes".
The difficulty with the FIG. 3 circuit is the discharge path for high-low transitions at the output. For example, as SELECT changes from high to low, diodes (34) and (36) eventually turn off as their forward bias is reduced. The dynamic impedance increases markedly, increasing the time constant for discharging capacitance at SELECT node.